The present invention relates to a semiconductor device, and more specifically, to a method of fabricating a metal oxide semiconductor field effect transistor (MOSFET) for used in deep sub-micron meter range.
The semiconductor industry has been advanced in an ever brisk pace, recently. In order to achieve high performance integrated circuits or high package density of a wafer, the sizes of semiconductor devices have become smaller and smaller than before in the field of Ultra Large Scale Integrated (ULSI) technologies. The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the metal-oxide-semiconductor transistor also follows the trend. As the size of the devices is scaled down, silicon based nano-scale electronics have been attention for these years. For example, single-electron-tunneling devices are developed in recent years.
Integrated circuits includes more than millions devices in a specific area of a wafer and electrically connecting structure for connecting these devices to perform desired function. One of the typical devices is metal oxide semiconductor field effect transistor (MOSFET). The MOSFET has been widely, traditionally applied in the semiconductor technologies. As the trend of the integrated circuits, the fabrication of the MOSFET also meets various issues to fabricate them. The typically issue that relates to hot carriers injection is overcame by the development of lightly doped drain (LDD) structure.
Further, the requirement of the devices towards high operation speed and low operation power. For deep sub-micron meter MOS devices, the self-aligned silicide (SALICIDE) contact, ultra-shallow source and drain junction are used for improving the operation speed and short channel effect. In another research by T. Yoshitomi, he develops a high performance CMOS with good control of short channel effect and silicide resistance. Please see xe2x80x9cHigh Performance 0.15 xcexcm Single Gate Co Salicide CMOS, T. Yoshitomi et al., 1996, Symposium on VLSI Technology Digest of Technical papersxe2x80x9d. The CoSi2, NiSi have been used for deep sub-micron high speed CMOS due to the low sheet resistance of fine silicide line. However, it is difficult to make ultra-shallow junction and form SALICIDE contact without degrading the device performance.
The requirement of the ULSI CMOS technology is the need of devices operated at low supply voltage and they have high speed. When the supply-voltage is reduced, the threshold voltage needs to be scaled down to achieve the desired circuit switching speed. IBM has proposed that CMOS employs non-uniform channel doping profiles and ultra-shallow source and drain extensions and halos, which can be referenced in xe2x80x9cCMOS technology scaling 0.1 xcexcm and beyond, IBM semiconductor research and development center, Bijan Davari, 1996, IEDM, 96-555xe2x80x9d. For the high performance case, the threshold voltage is scaled down less than the supply voltage in order to maintain a reasonable standby current.
U.S. Pat. No. 6,261,934 which assigned to Texas Instruments Incorporated (Dallas, Tex.), entitled xe2x80x9cDry etch process for small-geometry metal gates over thin gate dielectricxe2x80x9d discloses a structure for semiconductor device. As geometries shrink into the deep submicron regime (below 0.5 or 0.35 micron), such buried channels become very undesirable. Thus one of the constraints on new gate materials is a good work-function match to the semiconductor used. Titanium nitride is a very promising candidate for gate electrode material. It has a work function near the mid-gap point of silicon (4.65 eV) and eliminates gate depletion effects. However, titanium nitride has a quite high resistivity (120 m.OMEGA.-cm), and therefore needs to be used in conjunction with a material with higher conductivity for low interconnect delays to be achieved. For that purpose, tungsten (resistivity of 8 m.OMEGA.-cm) has been used.
The method of the present invention includes forming a dielectric layer on said semiconductor substrate. A dielectric layer is etched to form an opening in dielectric layer. A gate oxide layer is formed on semiconductor substrate in said opening. A barrier conductor is formed along the surface of the opening. A metal layer is formed on the barrier conductor and refilled into the opening. A portion of the metal layer and the barrier conductor is removed to form a gate for said transistor. The dielectric layer is removed. The barrier conductor is removed on sidewall of the gate. Lightly doped drain region is formed in the semiconductor substrate. Next, Sidewall spacer is formed on sidewall of the gate. Then, source and drain is formed in the semiconductor substrate by ion implantation using the gate and spacer as masking.